NXP Semiconductors /MIMXRT1052 /CCM /CCOSR

Selection of the clock to be generated on CCM_CLKO1

0 (CLKO1_SEL_0): USB1 PLL clock (divided by 2)

1 (CLKO1_SEL_1): SYS PLL clock (divided by 2)

3 (CLKO1_SEL_3): VIDEO PLL clock (divided by 2)

5 (CLKO1_SEL_5): semc_clk_root

10 (CLKO1_SEL_10): lcdif_pix_clk_root

11 (CLKO1_SEL_11): ahb_clk_root

12 (CLKO1_SEL_12): ipg_clk_root

13 (CLKO1_SEL_13): perclk_root

14 (CLKO1_SEL_14): ckil_sync_clk_root

15 (CLKO1_SEL_15): pll4_main_clk

Setting the divider of CCM_CLKO1

0 (CLKO1_DIV_0): divide by 1

1 (CLKO1_DIV_1): divide by 2

2 (CLKO1_DIV_2): divide by 3

3 (CLKO1_DIV_3): divide by 4

4 (CLKO1_DIV_4): divide by 5

5 (CLKO1_DIV_5): divide by 6

6 (CLKO1_DIV_6): divide by 7

7 (CLKO1_DIV_7): divide by 8

Enable of CCM_CLKO1 clock

0 (CLKO1_EN_0): CCM_CLKO1 disabled.

1 (CLKO1_EN_1): CCM_CLKO1 enabled.

CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks

0 (CLK_OUT_SEL_0): CCM_CLKO1 output drives CCM_CLKO1 clock

1 (CLK_OUT_SEL_1): CCM_CLKO1 output drives CCM_CLKO2 clock

Selection of the clock to be generated on CCM_CLKO2

3 (CLKO2_SEL_3): usdhc1_clk_root

5 (CLKO2_SEL_5): wrck_clk_root

6 (CLKO2_SEL_6): lpi2c_clk_root

11 (CLKO2_SEL_11): csi_clk_root

14 (CLKO2_SEL_14): osc_clk

17 (CLKO2_SEL_17): usdhc2_clk_root

18 (CLKO2_SEL_18): sai1_clk_root

19 (CLKO2_SEL_19): sai2_clk_root

20 (CLKO2_SEL_20): sai3_clk_root

23 (CLKO2_SEL_23): can_clk_root

27 (CLKO2_SEL_27): flexspi_clk_root

28 (CLKO2_SEL_28): uart_clk_root

29 (CLKO2_SEL_29): spdif0_clk_root

Setting the divider of CCM_CLKO2

0 (CLKO2_DIV_0): divide by 1

1 (CLKO2_DIV_1): divide by 2

2 (CLKO2_DIV_2): divide by 3

3 (CLKO2_DIV_3): divide by 4

4 (CLKO2_DIV_4): divide by 5

5 (CLKO2_DIV_5): divide by 6

6 (CLKO2_DIV_6): divide by 7

7 (CLKO2_DIV_7): divide by 8

Enable of CCM_CLKO2 clock

0 (CLKO2_EN_0): CCM_CLKO2 disabled.

1 (CLKO2_EN_1): CCM_CLKO2 enabled.